Method for self-aligning a stop layer to a replacement gate for self-aligned contact integration

ABSTRACT

Semiconductor devices with replacement gate electrodes and integrated self aligned contacts are formed with enhanced gate dielectric layers and improved electrical isolation properties between the gate line and a contact. Embodiments include forming a removable gate electrode on a substrate, forming a self aligned contact stop layer over the electrode and the substrate, removing a portion of the self aligned contact stop layer over the electrode and the electrode itself leaving an opening, forming a replacement gate electrode of metal, in the opening, transforming an upper portion of the metal into a dielectric layer, and forming a self aligned contact. Embodiments include forming the contact stop layer of a dielectric material, and transforming the upper portion of the metal into a dielectric layer. Embodiments also include forming a hardmask layer over the removable gate electrode to protect the electrode during silicidation in source/drain regions of the semiconductor device.

CROSS-REFERENCE TO RELATED APPLICATION

The present application is a divisional application of U.S. applicationSer. No. 12/561,708, filed on Sep. 17, 2009, the entire contents ofwhich are herein incorporated by reference.

TECHNICAL FIELD

The present disclosure relates to a method of fabricating semiconductordevices with metal gates and the resulting devices. The presentdisclosure is particularly applicable in fabricating semiconductordevices with metal replacement gates and self-aligned contacts.

BACKGROUND

The integration of hundreds of millions of circuit elements, such astransistors, on a single integrated circuit necessitates furtherdramatic scaling down or micro-miniaturization of the physicaldimensions of circuit elements, including interconnection structures.Micro-miniaturization has engendered a dramatic increase in transistorengineering complexity, such as the inclusion of lightly doped drainstructures, multiple implants for source/drain regions, silicidation ofgates and source/drains, and multiple sidewall spacers, for example.

The drive for high performance requires high speed operation ofmicroelectronic components requiring high drive currents in addition tolow leakage, i.e., low off-state current, to reduce power consumption.Typically, the structural and doping parameters tending to provide adesired increase in drive current adversely impact leakage current.

Metal gate electrodes have evolved for improving the drive current byreducing polysilicon depletion. However, simply replacing polysilicongate electrodes with metal gate electrodes may engender issues informing the metal gate electrode prior to high temperature annealing toactivate the source/drain implants, as at a temperature in excess of900° C. This fabrication technique may degrade the metal gate electrodeor cause interaction with the gate dielectric, thereby adverselyimpacting transistor performance.

Replacement gate techniques have been developed to address problemsattendant upon substituting metal gate electrodes for polysilicon gateelectrodes. For example, a polysilicon gate is used during initialprocessing until high temperature annealing to activate source/drainimplants has been implemented. Subsequently, the polysilicon is removedand replaced with a metal gate.

Additional issues arise with lateral scaling, such as the formation ofcontacts. For example, once the contacted poly pitch gets to about 80nanometers (nm), there is not enough room to land a contact between thegate lines and still maintain good electrical isolation propertiesbetween the gate line and the contact. Self aligned contact (SAC)methodology has been developed to address this problem. However,conventional SAC approaches involve metalizing the gate prior topatterning, followed by covering the gate with a hardmask to isolate thegate line from the contact during the contact etch and fill process.This approach, however, is not compatible with the replacement gateprocess.

A need therefore exists for methodology enabling the fabrication ofsemiconductor devices comprising integrating both metal replacementgates and self aligned contacts.

SUMMARY

An aspect of the present disclosure is an efficient method offabricating a semiconductor device with integrated self aligned contactsand replacement gate electrodes.

Another aspect of the present disclosure is a semiconductor devicecomprising integrated self aligned contacts and replacement gateelectrodes.

Additional aspects and other features of the present disclosure will beset forth in the description which follows and in part will be apparentto those having ordinary skill in the art upon examination of thefollowing or may be learned from the practice of the present disclosure.The advantages of the present disclosure may be realized and obtained asparticularly pointed out in the appended claims.

According to the present disclosure, some technical effects may beachieved in part by a method comprising: forming a removable gateelectrode over a substrate; forming an SAC stop layer over the removablegate electrode and the substrate; removing a portion of the SAC stoplayer over the removable gate electrode; removing the removable gateelectrode leaving an opening; forming a replacement gate electrode,comprising a metal, in the opening; transforming an upper portion of themetal into a dielectric layer; and forming an SAC.

Aspects of the present disclosure include forming spacers on sidesurfaces of the removable gate electrode, and forming the SAC stop layerover the spacers. Further aspects include transforming the upper portionof the metal into a dielectric layer by oxidation or nitridation, orfluorination. Another aspect includes anodizing an upper portion of themetal, which comprises aluminum, to form aluminum oxide (Al₂O₃).Additional aspects include forming devices wherein the SAC stop layercomprises a dielectric material, i.e., a hafnium oxide, an aluminumoxide, or a silicon carbide, for example a hafnium oxide. Aspects alsoinclude depositing the dielectric material by atomic layer deposition(ALD) or by chemical vapor deposition (CVD) at a thickness of about 1 toabout 10 nm. Further aspects include forming a hardmask layer on theremovable gate electrode, forming a contacted diffusion area spaced fromthe removable gate electrode by the spacers, and forming a silicide inthe area spaced from the removable gate electrode by the spacers, allprior to depositing the SAC stop layer. Another aspect includesproviding an isolation material filling a space in the area spaced fromthe removable gate electrode by the spacers after forming the SAC stoplayer, forming the replacement gate electrode, transforming the upperportion of the metal into a dielectric layer, and etching, with a highetch selectivity to the isolation material with respect to thedielectric layer, i.e., an etch selectivity of about 4:1 or greater, toremove the isolation material in order to form a contact hole.

Another aspect of the present disclosure is a semiconductor devicecomprising: a gate electrode, comprising a metal, over a substrate; anSAC stop layer over the substrate; a dielectric layer selectively formedfrom an upper portion of the metal gate electrode; and an SAC throughthe SAC stop layer and/or through the dielectric layer.

Aspects include spacers on side surfaces of the gate electrode, whereinthe SAC stop layer is over the spacers. Another aspect includessemiconductor devices wherein the dielectric layer comprising a nitrideor an oxide. Further aspects include semiconductor devices comprising analuminum replacement gate with a dielectric layer thereon comprisingaluminum oxide (Al₂O₃) formed by anodizing the aluminum. Additionalaspects include semiconductor devices wherein the SAC stop layercomprises a dielectric material, i.e., a hafnium oxide, an aluminumoxide, or a silicon carbide, for example a hafnium oxide. Other aspectsinclude semiconductor devices wherein a silicide is formed spaced fromthe gate electrode by the spacers under the SAC stop layer.

A further aspect of the present disclosure includes forming a first gateelectrode over a substrate, the first gate electrode comprising a high-Kgate dielectric layer, a metal layer on the gate dielectric layer, andpolysilicon; forming spacers on side surfaces of the first gateelectrode; forming a hardmask over the polysilicon; forming a silicideon the substrate; depositing an SAC stop layer over the hardmask layer,the spacers, and the silicide; depositing an isolation material over theSAC stop layer; forming a replacement gate electrode by: removing thehardmask layer and the polysilicon from the first gate electrode to forman opening; depositing a metal lining in the opening; and depositingaluminum on the metal lining in the opening; anodizing an upper portionof the aluminum to form a layer of aluminum oxide (Al₂O₃); etching, witha high etch selectivity to the isolation material with respect to theAl₂O₃ layer, to remove isolation material to form a contact hole and/orto remove the Al₂O₃ from the replacement gate electrode; and forming anSAC on the silicide and/or the replacement gate electrode.

Additional aspects and technical effects of the present disclosure willbecome readily apparent to those skilled in the art from the followingdetailed description wherein embodiments of the present disclosure aredescribed simply by way of illustration of the best mode contemplated tocarry out the present disclosure. As will be realized, the presentdisclosure is capable of other and different embodiments, and itsseveral details are capable of modifications in various obviousrespects, all without departing from the present disclosure.Accordingly, the drawings and description are to be regarded asillustrative in nature, and not as restrictive.

BRIEF DESCRIPTION OF THE DRAWINGS

The present disclosure is illustrated by way of example, and not by wayof limitation, in the figures of the accompanying drawing and in whichlike reference numerals refer to similar elements and in which:

FIGS. 1-3 schematically illustrate SAC process steps, according to anexemplary embodiment;

FIGS. 4-8 schematically illustrate replacement gate electrode processsteps, according to an exemplary embodiment; and

FIGS. 9A-9C schematically illustrate three different types of SACs,according to an exemplary embodiment.

DETAILED DESCRIPTION

In the following description, for the purposes of explanation, numerousspecific details are set forth in order to provide a thoroughunderstanding of exemplary embodiments. It should be apparent, however,that exemplary embodiments may be practiced without these specificdetails or with an equivalent arrangement. In other instances,well-known structures and devices are shown in block diagram form inorder to avoid unnecessarily obscuring exemplary embodiments.

The present disclosure addresses and solves the problem of degraded gatedielectrics and poor electrical isolation properties between the gateline and contacts that result from the use of metal gate electrodes andinsufficient space for etching contacts. In accordance with embodimentsof the present disclosure, a replacement gate electrode process isefficiently integrated with an SAC process. The use of a replacementgate electrode improves drive current without degrading the gatedielectric, while forming SACs improves electrical isolation propertiesbetween the gate line and the contact.

Embodiments of the present disclosure include forming a removable gateelectrode, e.g., of polysilicon, over a substrate. A high-K dielectriclayer and metal layer may be formed on the substrate under thepolysilicon. An SAC stop layer, e.g., a dielectric material, for examplea hafnium oxide, an aluminum oxide, or a silicon carbide, is formed overthe removable gate electrode and the substrate, e.g., by ALD or CVD at athickness of about 1 to about 10 nm. A portion of the SAC stop layerover the removable gate electrode and the removable gate electrodeitself are then removed, leaving an opening. A replacement gateelectrode, comprising a metal, is formed in the opening. A metal lining,corresponding to the metal previously deposited with the high-Kdielectric layer, may be formed in the opening prior to forming thereplacement gate electrode. An upper portion of the metal of thereplacement gate electrode is transformed into a dielectric layer, andan SAC is formed. In accordance with embodiments of the presentdisclosure, spacers may be formed on side surfaces of the removable gateelectrode, and the SAC stop layer may be formed over the spacers. Also,a hardmask layer may be formed on the removable gate electrode, asilicide may be formed in the area spaced from the removable gateelectrode by the spacers prior to depositing the SAC stop layer. Thetransformation of the upper portion of the metal into a dielectric maybe performed by oxidation or nitridation or fluorination. If, forexample, the metal of the replacement gate electrode comprises aluminum,the transformation may be implemented by anodizing an upper portion ofthe aluminum to form aluminum oxide (Al₂O₃). In addition, an isolationmaterial may be provided, e.g, by deposition, in the space between thegate electrodes after forming the SAC stop layer, and after transformingthe upper portion of the metal into the dielectric layer. The isolationmaterial may then be etched, with a high etch selectivity to theisolation material with respect to the dielectric layer, e.g., about 4:1to about 8:1, to remove the isolation material between the gateelectrodes to form the contact hole, and the SAC may be formed on thesilicide after removal of the SAC stop layer. Alternatively, oradditionally, the dielectric may be etched from the replacement gateelectrode and a contact may be formed on the replacement gate electrode.

A semiconductor device in accordance with embodiments of the presentdisclosure includes a gate electrode, comprising a metal, over asubstrate, and an SAC stop layer over the substrate. The device furtherincludes a dielectric layer selectively formed from an upper portion ofthe metal gate electrode, and a self aligned contact through the SACstop layer and/or through the dielectric layer. The device may includespacers on side surfaces of the gate electrode, such that the SAC stoplayer is over the spacers. The device may further include a silicidespaced from the gate electrode by the spacers under the SAC stop layer.The SAC stop layer may comprise a dielectric material, e.g., a hafniumoxide, an aluminum oxide, or a silicon carbide. The dielectric layer maycomprise a nitride or an oxide. If, for example, the metal of the gateelectrode comprises aluminum, the dielectric layer may comprise aluminumoxide (Al₂O₃) formed by anodizing the aluminum.

Still other aspects, features, and technical effects will be readilyapparent to those skilled in this art from the following detaileddescription, wherein preferred embodiments are shown and described,simply by way of illustration of the best mode contemplated. Thedisclosure is capable of other and different embodiments, and itsseveral details are capable of modifications in various obviousrespects. Accordingly, the drawings and description are to be regardedas illustrative in nature, and not as restrictive.

Adverting to FIG. 1, a method for forming a semiconductor, in accordancewith an exemplary embodiment, begins with a SAC process. A removablegate electrode 101, for example of polysilicon, is formed on gatedielectric layer 103, on a silicon substrate 105. Gate dielectric 103may be a high-K dielectric, for example having a dielectric constant ofabout 25 or greater, and a thin metal layer 111, e.g., of titaniumnitride (TiN), may be deposited on the gate dielectric layer 103. Anonconductive hardmask layer 107, such as a nitride, is formed on gateelectrode 101 to prevent the gate electrodes from being exposed duringlater source/drain silicidation. Sidewall spacers 109 are formed on bothsides of gate electrode 103 to encapsulate the gate electrode

As illustrated in FIG. 2, additional spacers 201 are formed on spacers109 to define the area for silicidation over source/drain regions of thesemiconductor device. Although only two sets of spacers (109 and 201)are shown, any number of spacers may be included. Next, a metal silicide203, e.g., nickel or nickel platinum silicide, is formed on substrate105 in the region between the spacers.

After the silicidation, an SAC stop layer 301 is conformally depositedover spacers 201 and 109, hardmask layer 107, and silicide 203, as shownin FIG. 3. SAC stop layer 301 may be, for example, a hafnium oxide(HfOx), an aluminum oxide, a silicon carbide, or any highly etchresistant dielectric material that is different from the spacers andexhibits good conformality. Stop layer 301 may be deposited to athickness of about 1 nm to about 10 nm, e.g., about 2 nm. An isolationmaterial, e.g. an oxide or an oxide plus a stress material, such as anitride, is deposited over the entire substrate to form isolation layer303.

Adverting to FIG. 4, the method continues with the replacement gateprocess. Isolation layer 303 and SAC stop layer 301 are polished, e.g.,by chemical mechanical polishing (CMP), down to hardmask layer 107.Alternatively, isolation layer 303 may be polished back to the stoplayer 301, and then the stop layer may be etched off, stopping athardmask layer 107.

After hardmask layer 107 is exposed, hardmask layer 107 and removablegate electrode 101 are removed, forming cavity 501, as illustrated inFIG. 5. Wet chemistry and/or a combination of dry and wet chemistriesmay be employed for removing hardmask layer 107 and removable gateelectrode 101.

As illustrated in FIG. 6, a metal lining 601, e.g., a TiN layer, is thenconformally deposited on isolation layer 303 and on the sidewalls andbottom surface of cavity 501 as a barrier layer. A metal layer 603,e.g., aluminum, is then deposited in cavity 501 and on metal lining 601.Metal layer 603 may alternatively be any metal, e.g., titanium, that canbe selectively grown into a dielectric material, e.g., by nitridation ordirect thermal oxidation. Metal layer 603 is then polished back to selfalign the replacement gate metal to the gate lines, thereby formingreplacement gate electrode 701, as illustrated in FIG. 7.

Adverting to FIG. 8, the top portion of metal layer 701 is nitrided,fluorinated, or oxidized to form dielectric layer 801. For an aluminum(Al) metal layer 701, the top portion may be anodized to form an Al₂O₃dielectric layer 801. Due to the nature of the annodization process, theAl₂O₃ formed is selective only to the gate layer. This completes thereplacement gate process. Capping layer 803, e.g., an interlayerdielectric, is then deposited over the entire surface to cap the gates,and the SAC process continues.

FIGS. 9A to 9C illustrate three different types of SACs formed accordingto an exemplary embodiment. Adverting to FIG. 9A, capping layer 803 andisolation layer 303 are etched to form the contact hole. FIG. 9Aindicates a misregistration of the contact hole 901 such that it landsover a portion of dielectric layer 801. The contact etch is preventedfrom reaching the gate electrode 701 and spacers 109 and 201 due to thehigh etch resistance of layers 801 and 301. Then the SAC stop layer 301is etched from the bottom of the contact hole to expose silicide 203. Acontact material fills the contact hole to form contact 901. During theetching of capping layer 803, dielectric layer 801 serves as a stoppingdielectric to isolate the contact from the gate lines, and SAC stoppinglayer 301 serves as an etch protect for the spacer sidewalls to allowsufficient dielectric thickness laterally between the contact and thegate.

In FIG. 9B, capping layer 803 and dielectric layer 801 are etched downto replacement gate electrode 701. The opening is filled with a contactmaterial to form a contact 902 to the gate line.

The processes exemplified in FIG. 9A and FIG. 9B can be combined. FIG.9C illustrates a gate to source/drain contact, i.e., an SRAMcross-coupling. As shown, capping layer 803 and dielectric layer 801 areetched down to replacement gate electrode 701, and capping layer 803,isolation layer 303, and SAC stop layer 301 are etched down to silicide203. The opening is then filled with a contact material to form contact903.

The embodiments of the present disclosure can achieve several technicaleffects, including improved drive current with degradation of the gatedielectric layer, and contacts with improved electrical isolationproperties between the gate line and the contact. The present disclosureenjoys industrial applicability in fabricating any of various types ofhighly integrated semiconductor devices, particularly with a gate pitchof about 80 nm or smaller.

In the preceding description, the present disclosure is described withreference to specifically exemplary embodiments thereof. It will,however, be evident that various modifications and changes may be madethereto without departing from the broader spirit and scope of thepresent disclosure, as set forth in the claims. The specification anddrawings are, accordingly, to be regarded as illustrative and not asrestrictive. It is understood that the present disclosure is capable ofusing various other combinations and embodiments and is capable of anychanges or modifications within the scope of the inventive concept asexpressed herein.

What is claimed is:
 1. A semiconductor device comprising: a gateelectrode, comprising a metal, over a substrate; an SAC stop layer overthe substrate; a dielectric layer selectively formed from an upperportion of the metal gate electrode; and an SAC through the SAC stoplayer and/or through the dielectric layer.
 2. The semiconductor deviceaccording to claim 1, further comprising spacers on side surfaces of thegate electrode, wherein the SAC stop layer is over the spacers.
 3. Thesemiconductor device according to claim 1, wherein the dielectric layercomprises a nitride or an oxide.
 4. The semiconductor device accordingto claim 3, wherein the metal comprises aluminum and the dielectriclayer comprises aluminum oxide (Al₂O₃) formed by anodizing the aluminum.5. The semiconductor device according to claim 1, wherein the SAC stoplayer comprises a dielectric material.
 6. The method according to claim5, wherein the dielectric material comprises a hafnium oxide, aluminumoxide, or a silicon carbide.
 7. The method according to claim 6, whereinthe dielectric material comprises a hafnium oxide.
 8. The semiconductordevice according to claim 2, further comprising: a substrate regionspaced from the gate electrode by the spacers; and a silicide formed inthe substrate region, under the SAC stop layer.